With a continuous scaling down of a size of a dynamic random access memory (DRAM) unit, an integration becomes higher and higher. On one hand, a difficulty in integrating one transistor and one capacitor together becomes higher and higher. On the other hand, due to the destructive reading and writing modes of the DRAM unit for stored information and short data retention time of the DRAM unit, a power consumption caused by refreshing may be continuously increased. Therefore, recently, a (1T) DRAM unit comprising one transistor without a capacitor has drawn extensive attention. Compared with a conventional (1T1C) DRAM unit comprising one transistor and one capacitor, the (1T) DRAM unit comprises one transistor without a capacitor, so the process is simpler and is compatible with a CMOS (complementary metal oxide semiconductor) process and the stored information may not be destroyed during the reading or writing. Thus, longer data retention time may be achieved.
FIG. 1 shows a schematic cross-sectional view of this (1T) DRAM unit. As shown in FIG. 1, this (1T) DRAM unit comprises: a substrate 011; an insulating buried layer 012 formed on the substrate 011; a source 013, a drain 014 and a body region 015 formed on the insulating buried layer 012 respectively, in which the body region 015 is formed between the source 013 and the drain 014; and a gate dielectric layer 016 formed on the body region 015, and a gate 017 formed on the gate dielectric layer 016. A p-type doped body region 015, an n-type doped source 013 and an n-type doped drain 014 are taken as an example. When the (1T) DRAM unit operates, holes generated by the (1T) DRAM unit are stored in an accumulation layer formed between the body region 015 and the insulating buried layer 012, in which the accumulation layer is next to the n-type doped source 013 and the n-type doped drain 014. The holes stored in this way may be easily collected by an off-state leakage current of the source 013 and the drain 014, and the stored holes may disappear quickly due to a carrier recombination effect. Therefore, a data retention time may be limited, thus narrowing an application field of the (1T) DRAM unit.